MC68HC912BD32 Datasheet, PDF (139/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Standard Timer Module
Timer Registers
Table 27 Prescaler Selection
PR2
PR1
PR0
Prescale
Factor
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
Reserved
1
1
1
Reserved
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
TFLG1 — Timer Interrupt Flag 1
$008E
Bit 7
6
5
4
3
2
1
Bit 0
C7F
C6F
C5F
C4F
C3F
C2F
C1F
C0F
RESET:
0
0
0
0
0
0
0
0
TFLG1 indicates when interrupt conditions have occurred. To clear a
bit in the flag register, write a one to the bit.
Read anytime. Write used in the clearing mechanism (set bits cause
corresponding bits to be cleared). Writing a zero will not effect current
status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture
or a write into an output compare channel ($90–$9F) will cause the
corresponding channel flag CnF to be cleared.
C7F–C0F — Input Capture/Output Compare Channel “n” Flag.
9-timer
Standard Timer Module
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MC68HC912BD32 Rev 1.0