MC68HC912BD32 Datasheet, PDF (143/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Standard Timer Module
Timer Registers
If the timer is not active (TEN = 0 in TSCR), there is no ÷64 clock since
the E÷64 clock is generated by the timer prescaler.
CLK1, CLK0 — Clock Select Register
Table 28 Clock Selection
CLK1
0
0
1
1
CLK0
0
1
0
1
Selected Clock
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock
from the timer is always used as an input clock to the timer counter.
The change from one selected clock to the other happens
immediately after these bits are written.
PAOVI — Pulse Accumulator Overflow Interrupt Enable
0 = Interrupt inhibited
1 = Interrupt requested if PAOVF is set
PAI — Pulse Accumulator Input Interrupt Enable
0 = Interrupt inhibited
1 = Interrupt requested if PAIF is set
PAFLG — Pulse Accumulator Flag Register
Bit 7
6
5
4
3
0
0
0
0
0
RESET:
0
0
0
0
0
$00A1
2
1
Bit 0
0
PAOVF PAIF
0
0
0
Read or write anytime.
When TFFCA bit in the TSCR register is set, any access to the
PACNT register will clear all the flags in the PAFLG register.
PAOVF — Pulse Accumulator Overflow Flag
Set when the 16-bit pulse accumulator overflows from $FFFF to
$0000. This bit is cleared automatically by a write to the PAFLG
register with bit 1 set.
13-timer
Standard Timer Module
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MC68HC912BD32 Rev 1.0