MC68HC912BD32 Datasheet, PDF (126/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pulse Width Modulator
Left-Aligned-Output Mode (CENTR = 0):
Duty cycle = [(PWDTYx + 1) / (PWPERx + 1)] × 100% (PPOLx = 1)
Duty cycle = [(PWPERx − PWDTYx) / (PWPERx + 1)] × 100%(PPOLx =
0)
Center-Aligned-Output Mode (CENTR = 1):
Duty cycle = [(PWPERx − PWDTYx) / PWPERx] × 100% (PPOLx = 1)
Duty cycle = (PWDTYx) / (PWPERx) × 100%(PPOLx = 0)
PWCTL— PWM Control Register
Bit 7
6
5
0
0
0
RESET:
0
0
0
4
PSWAI
0
3
CENTR
0
2
RDP
0
1
PUPP
0
$0054
Bit 0
PSBCK
0
Read and write anytime.
PSWAI — PWM Halts while in Wait Mode
0 = Allows PWM main clock generator to continue while in Wait
mode.
1 = Halt PWM main clock generator when the part is in Wait mode.
CENTR — Center-Aligned Output Mode
Program change of CENTR bit should be done when PWM channels
are disabled. All PWM counters should be written to as the last
operation before enabling the channels. Otherwise,
asserting/de-asserting the CENTR bit may cause irregularities in the
PWM output.
0 = PWM channels operate in Left-Aligned Output mode
1 = PWM channels operate in Center-Aligned Output mode
RDP — Reduced Drive of Port P
0 = All port P output pins have normal drive capability.
1 = All port P output pins have reduced drive capability.
PUPP — Pull-Up Port P Enable
0 = All port P pins have an active pull-up device disabled.
1 = All port P pins have an active pull-up device enabled.
MC68HC912BD32 Rev 1.0
Pulse Width Modulator
For More Information On This Product,
Go to: www.freescale.com
14-pwm