MC68HC912BD32 Datasheet, PDF (211/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Programmer’s Model
GISR
R
$xx07
W
H/S-RESET
BIT 7
TXIF
BIT 6
OVRNIF
BIT 5
ERRIF
BIT 4
SYNEIF
BIT 3
SYNLIF
BIT 2
ILLPIF
BIT 1
LOCKIF
0
0
0
0
0
0
0
Figure 43 General Interrupt Status Register (GISR)
BIT 0
WAKEIF
0
TXIF — Transmit Interrupt Flag
This read-only bit will be set when any of the enabled (IENAn = 1)
transmit buffers is empty. It can be cleared by clearing the IFLG bit(s)
of the corresponding buffer(s). After soft reset the flag is set if there is
at least one transmit buffer configured. If TXIE is set, a general
interrupt is pending while this flag is set.
1 = At least one transmit buffer is empty.
0 = All transmit buffers are full.
NOTE:
The TXIF flag is cleared two CPU cycles after clearing of all IFLG bits,
i.e. the application software should not read the TXIF flag immediately
after clearing the IFLG bit(s).
OVRNIF — Receive FIFO Overrun Interrupt Flag
This bit will be set when a Receive FIFO overrun occurred. If enabled,
a general interrupt is pending while this flag is set.
1 = A Receive FIFO overrun has been detected.
0 = No Receive FIFO overrun has occurred.
ERRIF — Message Format Error (CRC, Frame) Interrupt Flag
This bit will be set when a Message Format Error (CRC Error, Frame
Error) occurred. If enabled, a general interrupt is pending while this
flag is set.
1 = A Message Format Error has been detected.
0 = No Message Format Error has occurred.
SYNEIF — SYNC Pulse Too Early Error Interrupt Flag
This bit will be set when a SYNC pulse too early error appears. If
enabled, a general interrupt is pending while this flag is set.
1 = SYNC pulse to early error.
0 = No SYNC pulse to early error has occurred.
41-sibus
Byteflight™ Module
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MC68HC912BD32 Rev 1.0