MC68HC912BD32 Datasheet, PDF (114/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pulse Width Modulator
For Center Aligned mode two additional initialization operations occur:
the PWM counter is reset to $00 and a decision for the PWM output
value takes place. In this way the output of the PWM will always be; the
old waveform, or the new waveform and not some variation of the two.
The pulse modulated signal becomes available at port P output when the
PWM channel clock source begins its next cycle.
A change in duty or period can be forced into immediate effect by writing
the new value to the duty and/or period registers and then writing to the
counter. This causes the counter to reset and the new duty and/or period
values to be latched (this may cause a truncated PWM period). In
addition, since the counter is readable it is possible to know where the
count is with respect to the duty value and software can be used to make
adjustments by turning the enable bit off and on (only in Left Aligned
output mode).
MC68HC912BD32 Rev 1.0
Pulse Width Modulator
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