MC68HC912BD32 Datasheet, PDF (118/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pulse Width Modulator
PWM Register Description
PWCLK — PWM Clock Select Register with Concatenate Bits
Bit 7
6
5
4
3
2
CON23 CON01 PCKA2 PCKA1 PCKA0 PCKB2
RESET:
0
0
0
0
0
0
1
PCKB1
0
$0040
Bit 0
PCKB0
0
Read and write anytime.
CON23 — Concatenate PWM Channels 2 and 3
When concatenated, channel 2 becomes the high-order byte and
channel 3 becomes the low-order byte. Channel 2 output pin is used
as the output for this 16-bit PWM (bit 2 of port P). Channel 3
clock-select control bits determines the clock source.
0 = Channels 2 and 3 are separate 8-bit PWMs.
1 = Channels 2 and 3 are concatenated to create one 16-bit PWM
channel.
CON01 — Concatenate PWM Channels 0 and 1
When concatenated, channel 0 becomes the high-order byte and
channel 1 becomes the low-order byte. Channel 0 output pin is used
as the output for this 16-bit PWM (bit 0 of port P). Channel 1
clock-select control bits determines the clock source.
0 = Channels 0 and 1 are separate 8-bit PWMs.
1 = Channels 0 and 1 are concatenated to create one 16-bit PWM
channel.
NOTE:
These bits should be changed only when both corresponding channels
are disabled. For Left Aligned output mode operation when changing
these bits the user should write to the associated PWM counters as the
LAST operation before enabling (setting PWENx = q) the channel(s).
PCKA2–PCKA0 — Prescaler for Clock A
Clock A is one of two clock sources which may be used for channels
0 and 1. These three bits determine the rate of clock A, as shown in
Table 23.
MC68HC912BD32 Rev 1.0
Pulse Width Modulator
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6-pwm