MC68HC912BD32 Datasheet, PDF (231/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Analog to Digital Converter
ATD Registers
SCF — Sequence Complete Flag
This bit is set at the end of the conversion sequence when in the
single conversion sequence mode (SCAN = 0 in ATDCTL5) and is set
at the end of the first conversion sequence when in the continuous
conversion mode (SCAN = 1 in ATDCTL5). When AFFC = 0, SCF is
cleared when a write is performed to ATDCTL5 to initiate a new
conversion sequence. When AFFC = 1, SCF is cleared after the first
result register is read.
CC[2:0] — Conversion Counter for Current Sequence of Four or Eight
Conversions
This 3-bit value reflects the contents of the conversion counter pointer
in a four or eight count sequence. This value also reflects which result
register will be written next, indicating which channel is currently
being converted.
CCF[7:0] — Conversion Complete Flags
Each of these bits are associated with an individual ATD result
register. For each register, this bit is set at the end of conversion for
the associated ATD channel and remains set until that ATD result
register is read. It is cleared at that time if AFFC bit is set, regardless
of whether a status register read has been performed (i.e., a status
register read is not a pre-qualifier for the clearing mechanism when
AFFC = 1). Otherwise the status register must be read to clear the
flag.
ATDTSTH — ATD Test Register
$0068
RESET:
Bit 7
SAR9
0
6
SAR8
0
5
SAR7
0
4
SAR6
0
3
SAR5
0
2
SAR4
0
1
SAR3
0
Bit 0
SAR2
0
ATDTSTL — ATD Test Register
RESET:
Bit 7
SAR1
0
6
SAR0
0
5
RST
0
4
TSTOUT
0
3
TST3
0
2
TST2
0
1
TST1
0
Bit 0
TST0
0
$0069
9-adc
Analog to Digital Converter
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Go to: www.freescale.com
MC68HC912BD32 Rev 1.0