MC68HC912BD32 Datasheet, PDF (134/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Standard Timer Module
OC7M — Output Compare 7 Mask Register
Bit 7
6
5
4
OC7M7 OC7M6 OC7M5 OC7M4
RESET:
0
0
0
0
3
OC7M3
0
2
OC7M2
0
1
OC7M1
0
Bit 0
OC7M0
0
$0082
Read or write anytime.
The bits of OC7M correspond bit-for-bit with the bits of timer port
(PORTT). Setting the OC7Mn will set the corresponding port to be an
output port regardless of the state of the DDRTn bit when the
corresponding TIOSn bit is set to be an output compare. This does not
change the state of the DDRT bits.
OC7D — Output Compare 7 Data Register
Bit 7
6
5
4
OC7D7 OC7D6 OC7D5 OC7D4
RESET:
0
0
0
0
3
OC7D3
0
2
OC7D2
0
1
OC7D1
0
Bit 0
OC7D0
0
$0083
Read or write anytime.
The bits of OC7D correspond bit-for-bit with the bits of timer port
(PORTT). When a successful OC7 compare occurs, for each bit that
is set in OC7M, the corresponding data bit in OC7D is stored to the
corresponding bit of the timer port.
When the OC7Mn bit is set, a successful OC7 action will override a
successful OC[6:0] compare action during the same cycle; therefore,
the OCn action taken will depend on the corresponding OC7D bit.
TCNT — Timer Count Register
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
RESET:
0
0
0
0
0
0
$0084–$0085
1
Bit 0
9
Bit 8
1
Bit 0
0
0
A full access for the counter register should take place in one clock
cycle. A separate read/write for high byte and low byte will give a
different result than accessing them as a word.
Read anytime.
MC68HC912BD32 Rev 1.0
Standard Timer Module
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Go to: www.freescale.com
4-timer