MC68HC912BD32 Datasheet, PDF (206/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
FIFO Size Register
(FSIZR)
BIT 7
FSIZR R
0
$xx01 W
RESET
0
BIT 6
0
BIT 5
0
BIT 4
FSIZ4*
BIT 3
FSIZ3*
BIT 2
FSIZ2*
0
0
0
0
0
Figure 38 FIFO Size Register (FSIZR)
BIT 1
FSIZ1*
0
BIT 0
FSIZ0*
0
FSIZ4:0 — FIFO Size Bits
These bits are used to configure the FIFO. The number of buffers,
starting from buffer ‘0’, assigned to the receive FIFO can be selected.
The corresponding buffer(s) must be assigned as Receive buffer by
the CFG-bits in the message buffer control register(s).
Table 46 FIFO Size
FSIZ[4:0]
0 0000
0 0001
0 0010
0 0011
:
01111
10000
11111
FIFO Size
No FIFO
buffer 0
buffers 0, 1
buffers 0- 2
:
buffers 0-14
buffers 0-15
buffers 0-15
buffers 0-15
NOTE: The FSIZR register can only be written if the SFTRES bit in the Module
Configuration register is set.
MC68HC912BD32 Rev 1.0
Byteflight™ Module
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36-sibus