MC68HC912BD32 Datasheet, PDF (165/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Interface
Serial Peripheral Interface (SPI)
LSBF — SPI LSB First enable
0 = Data is transferred most significant bit first
1 = Data is transferred least significant bit first
Normally data is transferred most significant bit first.This bit does not
affect the position of the MSB and LSB in the data register. Reads and
writes of the data register will always have MSB in bit 7.
SP0CR2 — SPI Control Register 2
$00D1
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
SSWAI SPC0
RESET:
0
0
0
0
0
0
0
0
Read or write anytime.
SSWAI — SSI Stop in Wait Mode
0 = SSI clock operate normally
1 = Halt SSI clock generation when in Wait mode
SPC0 — Serial Pin Control 0
This bit decides serial pin configurations with MSTR control bit.
Table 32
Pin Mode
#1
Normal
#2
#3
Bidirectional
#4
SPC0⁽¹⁾
0
1
MSTR
0
1
0
1
MISO⁽²⁾
Slave Out
Master In
Slave I/O
GPI/O
MOSI⁽³⁾
Slave In
Master Out
GPI/O
Master I/O
1. The serial pin control 0 bit enables bidirectional configurations.
2. Slave output is enabled if DDS4 = 1, SS = 0 and MSTR = 0. (#1, #3)
3. Master output is enabled if DDS5 = 1 and MSTR = 1. (#2, #4)
4. SCK output is enabled if DDS6 = 1 and MSTR = 1. (#2, #4)
5. SS output is enabled if DDS7 = 1, SSOE = 1 and MSTR = 1. (#2, #4)
SCK⁽⁴⁾
SCK In
SCK Out
SCK In
SCK Out
SS⁽⁵⁾
SS In
SS I/O
SS In
SS I/O
19-sint
Serial Interface
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Go to: www.freescale.com
MC68HC912BD32 Rev 1.0