MC68HC912BD32 Datasheet, PDF (97/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Resets and Interrupts
Resets
HPRIO — Highest Priority I Interrupt
Bit 7
6
5
1
1
PSEL5
RESET:
1
1
1
4
PSEL4
1
3
PSEL3
0
2
PSEL2
0
1
PSEL1
1
$001F
Bit 0
0
0
Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime.
To give a maskable interrupt source highest priority, write the low byte
of the vector address to the HPRIO register. For example, writing $F0 to
HPRIO would assign highest maskable interrupt priority to the real-time
interrupt timer ($FFF0). If an unimplemented vector address or a
non-I-masked vector address (value higher than $F2) is written, then
IRQ will be the default highest priority interrupt.
Resets
There are four possible sources of reset. Power-on reset (POR), and
external reset on the RESET pin share the normal reset vector. The
computer operating properly (COP) reset and the clock monitor reset
each has a vector. Entry into reset is asynchronous and does not require
a clock but the MCU cannot sequence out of reset without a system
clock.
Power-On Reset
A positive transition on V_DD causes a power-on reset (POR). An external
voltage level detector, or other external reset circuits, are the usual
source of reset in a system. The POR circuit only initializes internal
circuitry during cold starts and cannot be used to force a reset as system
voltage drops.
External Reset
5-resets
The CPU distinguishes between internal and external reset conditions
by sensing whether the reset pin rises to a logic one in less than eight
E-clock cycles after an internal device releases reset. When a reset
condition is sensed, the RESET pin is driven low by an internal device
for about 16 E-clock cycles, then released. Eight E-clock cycles later it
is sampled. If the pin is still held low, the CPU assumes that an external
Resets and Interrupts
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MC68HC912BD32 Rev 1.0