MC68HC912BD32 Datasheet, PDF (153/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Interface
Serial Communication Interface (SCI)
Table 30 Loop Mode Functions
LOOPS RSRC
0
x
1
0
1
0
1
0
DDS1(3)
x
0
1
1
WOMS
x
0/1
0
1
1
1
0
x
1
1
1
0
1
1
1
1
Function of Port S Bit 1/3
Normal Operations
LOOP mode without TXD output (TXD = High Impedance)
LOOP mode with TXD output (CMOS)
LOOP mode with TXD output (open-drain)
Single wire mode without TXD output
(the pin is used as receiver input only, TXD = High Impedance)
Single wire mode with TXD output
(the output is also fed back to receiver input, CMOS)
Single wire mode for the receiving and transmitting (open-drain)
M — Mode (select character format)
0 = One start, eight data, one stop bit
1 = One start, eight data, ninth data, one stop bit
WAKE — Wakeup by Address Mark/Idle
0 = Wake up by IDLE line recognition
1 = Wake up by address mark (last data bit set)
ILT — Idle Line Type
Determines which of two types of idle line detection will be used by
the SCI receiver.
0 = Short idle line mode is enabled.
1 = Long idle line mode is detected.
In the short mode, the SCI circuitry begins counting ones in the search
for the idle line condition immediately after the start bit. This means
that the stop bit and any bits that were ones before the stop bit could
be counted in that string of ones, resulting in earlier recognition of an
idle line.
In the long mode, the SCI circuitry does not begin counting ones in the
search for the idle line condition until a stop bit is received. Therefore,
the last byte’s stop bit and preceding “1” bits do not affect how quickly
an idle line condition can be detected.
PE — Parity Enable
0 = Parity is disabled.
1 = Parity is enabled.
7-sint
MC68HC912BD32 Rev 1.0
Serial Interface
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