MC68HC912BD32 Datasheet, PDF (203/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Programmer’s Model
GETIDX is incremented when unlocking the FIFO by writing a ‘0’ to
the lock bit of buffer 0. Locking a buffer other than buffer 0 within the
FIFO does not influence the FIFO window scheme.
NOTE:
The lock request is stored, i.e. only one write is necessary. Internal
synchronization takes up to two CPU cycle to update the LOCK bit, i.e.
the application software should access a locked buffer after verifying the
lock bit
IENA — Interrupt Enable Bit
This bit enables the corresponding buffer as interrupt source.
1 = The corresponding buffer interrupt enabled.
0 = The corresponding buffer interrupt disabled.
IFLG — Interrupt Status Flag
This flag has various functions depending on the configuration of the
corresponding message buffer.
If the buffer is configured as receive buffer this flag indicates that the
buffer is full. The status flag is cleared if a ‘1’ is written to the bit
position. The soft reset value is ‘0’.
1 = Flag set when the receive buffer is full.
0 = Flag cleared when the receive buffer is empty.
If the buffer is configured as transmit buffer this flag indicates that the
buffer is empty. The status flag is cleared if a ‘1’ is written to the bit
position. The soft reset value is ‘1’.
1 = Flag set when the transmit buffer is empty (i.e. has been
transmitted or has been aborted).
0 = Flag cleared when the transmit buffer is full and ready for
transmit.
If the buffer is configured as receive FIFO buffer this flag has no
meaning. It will never be set. The soft reset value is ‘0’.
33-sibus
Byteflight™ Module
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MC68HC912BD32 Rev 1.0