MC68HC912BD32 Datasheet, PDF (201/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Programmer’s Model
Addr
Register Name
$xxx0
Identifier Register
$xxx1 Data Length Register (4 msb reserved)
$xxx2
Data Register 0
$xxx3
Data Register 1
$xxx4
Data Register 2
$xxx5
Data Register 3
$xxx6
Data Register 4
$xxx7
Data Register 5
$xxx8
Data Register 6
$xxx9
Data Register 7
$xxxA
Data Register 8
$xxxB
Data Register 9
$xxxC
Data Register 10
$xxxD
Data Register 11
$xxxE
reserved
$xxxF
reserved
Figure 34 Message Buffer Organization
Message Buffer
Control Registers
(BUFCTL15..0)
Each of the 16 configurable message buffers is associated with one
Buffer Control Register. All 16 registers are addressable by the CPU.
Only a hard reset will clear the register.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BUFCTLn R
ABTAK
0
0
IFLG
IENA
LOCK
ABTRQ
W
HARDRESET
0
0
0
0
0
0
0
Figure 35 Message Buffer Control Registers (BUFCTL15:BUFCTL0)
BIT 0
CFG*
0
CFG — Message Buffer Configuration Bit
This bit is used to configure the corresponding buffer as transmit
buffer or as receive or receive FIFO buffer. This bit is readable and is
only cleared by hard reset. Writing to this bit is allowed during soft
reset only.
1 = The corresponding buffer is configured as transmit buffer.
0 = The corresponding buffer is configured as receive buffer or
receive FIFO buffer.
31-sibus
Byteflight™ Module
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MC68HC912BD32 Rev 1.0