MC68HC912BD32 Datasheet, PDF (258/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Development Support
begun by the time an operation is visible outside the MCU. A separate
instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for
tagging. The TAGLO signal shares a pin with the LSTRB signal, and the
TAGHI signal shares a pin with the BKGD signal. Tagging information is
latched on the falling edge of ECLK.
Table 64 shows the functions of the two tagging pins. The pins operate
independently - the state of one pin does not affect the function of the
other. The presence of logic level zero on either pin at the fall of ECLK
performs the indicated function. Tagging is allowed in all modes.
Tagging is disabled when BDM becomes active and BDM serial
commands are not processed while tagging is active.
Table 64 Tag Pin Function
TAGHI
1
1
0
0
TAGLO
1
0
1
0
Tag
no tag
low byte
high byte
both bytes
The tag follows program information as it advances through the queue.
When a tagged instruction reaches the head of the queue, the CPU
enters active background debugging mode rather than execute the
instruction.
MC68HC912BD32 Rev 1.0
Development Support
For More Information On This Product,
Go to: www.freescale.com
24-dev