MC68HC912BD32 Datasheet, PDF (166/292 Pages) Freescale Semiconductor, Inc – Advance Information

Serial Interface
Freescale Semiconductor, Inc.
SP0BR — SPI Baud Rate Register
Bit 7
6
5
4
0
0
0
0
RESET:
0
0
0
0
3
2
1
Bit 0
0
SPR2 SPR1 SPR0
0
0
0
0
Read anytime. Write anytime.
At reset, E Clock divided by 2 is selected.
SPR[2:0] — SPI Clock (SCK) Rate Select Bits
These bits are used to specify the SPI clock rate.
$00D2
SPR2
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
Table 33 SPI Clock Rate Selection
SPR0
0
1
0
1
0
1
0
1
E Clock
Divisor
2
4
8
16
32
64
128
256
Frequency at Frequency at
Frequency at
E Clock = 4 MHz E Clock = 8 MHz E Clock = 10 MHz
2.0 MHz
4.0 MHz
5.0 MHz
1.0 MHz
2.0 MHz
2.5 MHz
500 KHz
1.0 MHz
1.25 MHz
250 KHz
500 KHz
625 KHz
125 KHz
250 KHz
313 KHz
62.5 KHz
125 KHz
156 KHz
31.3 KHz
62.5 KHz
78.1 KHz
15.6 KHz
31.3 KHz
39.1 KHz
SP0SR — SPI Status Register
$00D3
Bit 7
6
5
4
3
2
1
Bit 0
SPIF WCOL
0
MODF
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
Read anytime. Write has no meaning or effect.
SPIF — SPI Interrupt Request
SPIF is set after the eighth SCK cycle in a data transfer and it is
cleared by reading the SP0SR register (with SPIF set) followed by an
access (read or write) to the SPI data register.
MC68HC912BD32 Rev 1.0
Serial Interface
For More Information On This Product,
Go to: www.freescale.com
20-sint