MC68HC912BD32 Datasheet, PDF (242/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
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The second type of BDM commands are called firmware commands
implemented in a small ROM within the HC12 MCU.The CPU must be in
background mode to execute firmware commands. The usual way to get
to background mode is by the hardware command BACKGROUND. The
BDM ROM is located at $FF20 to $FFFF while BDM is active. There are
also seven bytes of BDM registers located at $FF00 to $FF06 while BDM
is active. The CPU executes code in the BDM firmware to perform the
requested operation. The BDM firmware watches for serial commands
and executes them as they are received. The firmware commands are
shown in Table 57.
Command
READ_NEXT
READ_PC
READ_D
READ_X
READ_Y
READ_SP
WRITE_NEXT
WRITE_PC
WRITE_D
WRITE_X
WRITE_Y
WRITE_SP
GO
TRACE1
TAGGO
Table 57 BDM Firmware Commands
Opcode
(Hex)
62
63
64
65
66
67
42
43
44
45
46
47
08
10
18
Data
Description
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data in
16-bit data in
16-bit data in
16-bit data in
16-bit data in
16-bit data in
None
None
None
X = X + 2; Read next word pointed to by X
Read program counter
Read D accumulator
Read X index register
Read Y index register
Read stack pointer
X = X + 2; Write next word pointed to by X
Write program counter
Write D accumulator
Write X index register
Write Y index register
Write stack pointer
Go to user program
Execute one user instruction then return to BDM
Enable tagging and go to user program
Each of the hardware and firmware BDM commands start with an 8-bit
command code (opcode). Depending upon the commands, a 16-bit
address and/or a 16-bit data word is required as indicated in the tables
by the command. All the read commands output 16-bits of data despite
the byte/word implication in the command name.
The external host should wait 150 BCLK cycles for a non-intrusive BDM
command to execute before another command is sent. This delay
includes 128 BCLK cycles for the maximum delay for a free cycle.For
MC68HC912BD32 Rev 1.0
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