MC68HC912BD32 Datasheet, PDF (144/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Standard Timer Module
PAIF — Pulse Accumulator Input Edge Flag
Set when the selected edge is detected at the pulse accumulator
input pin. In event mode, the event edge triggers PAIF. In gated time
accumulation mode, the trailing edge of the gate signal at the pulse
accumulator input pin triggers PAIF. This bit is cleared automatically
by a write to the PAFLG register with bit 0 set.
PACNT — 16-bit Pulse Accumulator Count Register
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
RESET:
0
0
0
0
0
0
$00A2–$00A3
1
Bit 0
9
Bit 8
1
Bit 0
0
0
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different
result than accessing them as a word.
Read or write anytime.
TIMTST — Timer Test Register
$00AD
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
TCBYP PCBYP
RESET:
0
0
0
0
0
0
0
0
Read anytime. Write only in special mode (SMODN = 0)
TCBYP — Timer Divider Chain Bypass
0 = Normal operation
1 = The 16-bit free-running timer counter is divided into two 8-bit
halves and the prescaler is bypassed. The clock drives both
halves directly.
PCBYP — Pulse Accumulator Divider Chain Bypass
0 = Normal operation
1 = The 16-bit pulse accumulator counter is divided into two 8-bit
halves and the prescaler is bypassed. The clock drives both
halves directly.
MC68HC912BD32 Rev 1.0
Standard Timer Module
For More Information On This Product,
Go to: www.freescale.com
14-timer