MC68HC912BD32 Datasheet, PDF (227/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Analog to Digital Converter
ATD Registers
Table 51 ATD Response to Background Debug Enable
FRZ1
0
0
1
1
FRZ0
0
1
0
1
ATD Response
Continue conversions in active background mode
Reserved
Finish current conversion, then freeze
Freeze when BDM is active
ATDCTL4 — ATD Control Register 4
$0064
RESET:
Bit 7
S10BM
0
6
SMP1
0
5
SMP0
0
4
PRS4
0
3
PRS3
0
2
PRS2
0
1
PRS1
0
Bit 0
PRS0
1
The ATD control register 4 is used to select the clock source and set
up the prescaler. Writes to the ATD control registers initiate a new
conversion sequence. If a write occurs while a conversion is in
progress, the conversion is aborted and ATD activity halts until a write
to ATDCTL5 occurs.
S10BM — ATD 10-bit Mode Control
0 = 8 bit operation
1 = 10 bit operation
SMP1
0
0
1
1
SMP0
0
1
0
1
SMP1, SMP0 — Select Sample Time
These bits are used to select one of four sample times after the
buffered sample and transfer has occurred.
Table 52 Final Sample Time Selection
Final Sample Time
2 ATD clock periods
4 ATD clock periods
8 ATD clock periods
16 ATD clock periods
Total 8-Bit Conversion Time
18 ATD clock periods
20 ATD clock periods
24 ATD clock periods
32 ATD clock periods
Total 10-Bit Conversion Time
20 ATD clock periods
22 ATD clock periods
26 ATD clock periods
34 ATD clock periods
PRS4, PRS3, PRS2, PRS1, PRS0 — Select Divide-By Factor for ATD
P-Clock Prescaler.
The binary value written to these bits (1 to 31) selects the divide-by
factor for the modulo counter-based prescaler. The P clock is divided
by this value plus one and then fed into a ÷2 circuit to generate the
5-adc
Analog to Digital Converter
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MC68HC912BD32 Rev 1.0