MC68HC912BD32 Datasheet, PDF (32/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
When the PUPE bit in the PUCR register is set, PE[7,3,2,1,0] are pulled
up. PE[7,3,2,1,0] are pulled up active devices, while PE1 is always
pulled up by means of an internal resistor.
Neither port E nor DDRE is in the map in peripheral mode; neither is in
the internal map in expanded modes with EME set.
Setting the RDPE bit in register RDRIV causes all port E outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to Bus Control and
Input/Output.
Port SBI
The port SBI has four general-purpose I/O pins, PSBI[5:2]. The DIVBYP
pin, the Byteflight™ receive pin, Rx, and transmit pin, Tx, cannot be
configured as general-purpose I/O on port SBI.
Register DDRSBI determines whether each port SBI pin PSBI[5:2] is an
input or output. Setting a bit in DDRSBI makes the corresponding pin in
port SBI an output; clearing a bit makes the corresponding pin an input.
After reset port SBI pins PSBI[5:2] are configured as inputs.
When a read to the port SBI is performed, the values for Bit 7 and Bit 6
depend on the contents of the port SBI data register, PORTSBI[7:6] and
the of contents of DDRSBI[7:6]. Refer to Table 6 for the returned values.
Table 6 Port SBI Read accesses
DDRSBI[Bit x]
0
1
Bit 7
0
PORTSBI[7]
Read data values
Bit 6
DIVBYP
PORTSBI[6]
Bit 5... Bit 2
PSBI[5:2]
PORTSBI[5:2]
When the PUESBI bit in the PCTLSBI register is set, port SBI input pins
PSBI[5:2] are pulled up internally by an active pull-up device.
Setting the RDRSBI bit in register PCTLSBI causes the port SBI outputs
PSBI[5:2] to have reduced drive level. Levels are at normal drive
capability after reset. RDRSBI can be written anytime after reset. Refer
to Byteflight™ Module.
MC68HC912BD32 Rev 1.0
Pinout and Signal Descriptions
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12-pins