MC68HC912BD32 Datasheet, PDF (125/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Pulse Width Modulator
PWM Register Description
value is written. Reading this register returns the most recent value
written. When in concatenated mode, the new period should be
written with a 16-bit access to both channels registers (0 & 1, or 2 &
3) for data coherency. To start a new period immediately, write the
new period value and then write the counter forcing a new period to
start with the new period value.
Period = [Channel-Clock-Period x (PWPER + 1)](CENTR = 0)
Period = [Channel-Clock-Period × (PWPER x 2)](CENTR = 1)
NOTE: For Boundary Case programming values please refer to PWM Boundary
Cases.
PWDTYx — PWM Channel Duty Registers
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY0 Bit 7
6
5
4
3
2
1
Bit 0
$0050
PWDTY1 Bit 7
6
5
4
3
2
1
Bit 0
$0051
PWDTY2 Bit 7
6
5
4
3
2
1
Bit 0
$0052
PWDTY3 Bit 7
6
5
4
3
2
1
Bit 0
$0053
RESET
1
1
1
1
1
1
1
1
Read and write anytime.
The value in each duty register determines the duty of the associated
PWM channel. The duty value is compared to the counter and if it is
equal to the counter value a match occurs and he output changes
state. If the register is written to while the channel is enabled, then the
new value is held in the buffer until the counter reaches zero or the
channel is disabled and re-enabled. When in concatenated mode the
new period should be written to both channels registers (0 & 1, or 2 &
3) with a 16 bit access for data coherency. Reading this register
returns the most recent value written.
NOTE: For Boundary Case programming values please refer to PWM Boundary
Cases.
13-pwm
Pulse Width Modulator
For More Information On This Product,
Go to: www.freescale.com
MC68HC912BD32 Rev 1.0