MC68HC912BD32 Datasheet, PDF (112/292 Pages) Freescale Semiconductor, Inc – Advance Information

Clocks
Freescale Semiconductor, Inc.
PCLK
REGISTER: TMSK2
TEN _{BITS: PR2, PR1, PR0}
0:0:0
REGISTER: PACTL
BITS: PAEN, CLK1, CLK0
0:x:x
÷2
0:0:1
1:0:0
÷2
0:1:0
1:0:1
÷2
÷2
÷2
÷2
PORT T7
PAEN
0:1:1
1:0:0
1:0:1
GATE
LOGIC
PAMOD
PACLK
PULSE ACC
LOW BYTE
PACLK/256
1:1:0
1:1:1
PACLK/65536
(PAOV)
PULSE ACC
HIGH BYTE
TO TIM
COUNTER
Figure 13 Clock Chain for TIM
PCLK
5-BIT MODULUS
COUNTER (PR0-PR4)
÷2
÷2
REGISTER: SP0BR
BITS: SPR2, SPR1, SPR0
0:0:0
÷2
0:0:1
SPI
BIT RATE
TO ATD
÷2
0:1:0
÷2
0:1:1
÷2
1:0:0
÷2
1:0:1
÷2
1:1:0
÷2
1:1:1
ECLK
SYNCHRONIZER
BKGD IN
BKGD
PIN
LOGIC
BKGD DIRECTION
BKGD OUT
BDM BIT CLOCK:
Receive: Detect falling edge,
count 12 E clocks, Sample input
Transmit 1: Detect falling edge,
count 6 E clocks while output is
high impedance, Drive out 1 E
cycle pulse high, high imped-
ance output again
Transmit 0: Detect falling edge,
Drive out low, count 9 E clocks,
Drive out 1 E cycle pulse high,
high impedance output
Figure 14 Clock Chain for SPI, ATD and BDM
MC68HC912BD32 Rev 1.0
Clocks
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12-clock