MC68HC912BD32 Datasheet, PDF (156/292 Pages) Freescale Semiconductor, Inc – Advance Information

Serial Interface
Freescale Semiconductor, Inc.
transmit related bits in SC0SR1 (TDRE and TC) are cleared by a read
of the SC0SR1 register followed by a write to the transmit/receive
data register L.
Read anytime (used in auto clearing mechanism). Write has no
meaning or effect.
TDRE — Transmit Data Register Empty Flag
New data will not be transmitted unless SC0SR1 is read before writing
to the transmit data register. Reset sets this bit.
0 = SC0DR busy
1 = Any byte in the transmit data register is transferred to the serial
shift register so new data may now be written to the transmit
data register.
TC — Transmit Complete Flag
Flag is set when the transmitter is idle (no data, preamble, or break
transmission in progress). Clear by reading SC0SR1 with TC set and
then writing to SC0DR.
0 = Transmitter busy
1 = Transmitter is idle
RDRF — Receive Data Register Full Flag
Once cleared, IDLE is not set again until the RxD line has been active
and becomes idle again. RDRF is set if a received character is ready
to be read from SC0DR. Clear the RDRF flag by reading SC0SR1
with RDRF set and then reading SC0DR.
0 = SC0DR empty
1 = SC0DR full
IDLE — Idle Line Detected Flag
Receiver idle line is detected (the receipt of a minimum of 10/11
consecutive ones). This bit will not be set by the idle line condition
when the RWU bit is set. Once cleared, IDLE will not be set again until
after RDRF has been set (after the line has been active and becomes
idle again).
0 = RxD line is idle
1 = RxD line is active
MC68HC912BD32 Rev 1.0
Serial Interface
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