MC68HC912BD32 Datasheet, PDF (219/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Byteflight™ Module
Programmer’s Model
PSYNEN — Sync Pulse Enable
1 = A 50ns pulse is driven on Port SBI2 after the successful
reception or transmission of a sync pulse.
0 = Port SBI2 is a general IO pin.
PUESBI — Pull Up Enable Port SBI
1 = Pull up enabled for Port SBI.
0 = Pull up disabled for Port SBI.
RDRSBI — Reduced Drive Port SBI
1 = Reduced drive enabled for Port SBI.
0 = Reduced drive disabled for Port SBI.
Byteflight™ Port
SBI Data Register
(PORTSBI
PORTSBI R
$xx11
W
HARDRESET
BIT 7
PSBI7
U
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
PSBI6
PSBI5
PSBI4
PSBI3
PSBI2
U
U
U
U
U
Figure 53 Port SBI Data Register (PORTSBI)
BIT 1
TX
U
BIT 0
RX
U
PSBI7 – PSBI2 — Port SBI Data Bits
Writing to PSBIx stores the bit value in an internal bit memory. This
value is driven to the respective pin only if DDRSBIx = 1. Only a hard
reset will clear the register.
Reading PSBIx returns
• the value of the internal bit memory driven to the pin, if DDRSBIx
=1
• the value of the respective pin, if DDRSBIx = 0
Reading bits 1 and 0 returns the value of the Tx and Rx pins,
respectively.
49-sibus
Byteflight™ Module
For More Information On This Product,
Go to: www.freescale.com
MC68HC912BD32 Rev 1.0