UPSD3354DV-40U6 Datasheet, PDF (99/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Standard 8032 timer/counters
Figure 23. Timer/Counter mode 3: Two 8-bit counters
f_OSC
C0 pin
÷ 12
C/T = 0
C/T = 1
Control
TL0
(8 bits)
TR0
Gate
EXTINT0 pin
f_OSC
÷ 12
Control
TH0
(8 bits)
TF0
Interrupt
TF1
Interrupt
TR1
AI06624
t(s) 20.6
Obsolete ^{Product(s) - Obsolete Produc 20.6.1}
Timer 2
Timer 2 can operate as either an event timer or as an event counter. This is selected by the
bit C/T2 in the SFR named, T2CON (Table 58 on page 100). Timer 2 has three operating
modes selected by bits in T2CON, according to Table 60 on page 101. The three modes
are:
● Capture mode
● Auto re-load mode
● Baud rate generator mode
Capture mode
In Capture mode there are two options which are selected by the bit EXEN2 in T2CON.
Figure 24 on page 104 illustrates Capture mode.
If EXEN2 = 0, then Timer 2 is a 16-bit timer if C/T2 = 0, or it’s a 16-bit counter if C/T2 = 1,
either of which sets the interrupt flag bit TF2 upon overflow.
If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0
transition at external input pin T2X causes the current value in the Timer 2 registers, TL2
and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the
transition at T2X causes interrupt flag bit EXF2 in T2CON to be set. Either flag TF2 or EXF2
will generate an interrupt and the MCU must read both flags to determine the cause. Flags
TF2 and EXF2 are not automatically cleared by hardware, so the firmware servicing the
interrupt must clear the flag(s) upon exit of the interrupt service routine.
Doc ID 9685 Rev 7
99/272