UPSD3354DV-40U6 Datasheet, PDF (120/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

IrDA interface
UPSD33xx
Figure 36. Pulse shaping by the IrDA interface
Start
Bit
UART Frame
Data Bits
Stop
Bit
0
1
0
1
0
0
1
1
0
1
Start
Bit
UART Frame
IR Frame
Data Bits
Stop
Bit
0
1
0
1
0
0
1
1
0
1
t(s) ^{Bit Time}
IR Frame
Pulse Width = 3/16 Bit Time
AI09624b
duc The UART1 serial channel can operate in one of four different modes as shown in Table 62
ro ^{on page 107 in Section 21: Serial UART interfaces on page 106. However, when UART1 is}
P ^{used for IrDA communication, UART1 must operate in mode 1 only, to be compatible with}
IrDA protocol up to 115.2k bps. The IrDA interface will support baud rates generated from
te _{Timer 1 or Timer 2, just like standard UART serial communication, but with one restriction.}
le _{The transmit baud rate and receive baud rate must be the same (cannot be different rates as}
o _{is allowed by standard UART communications).}
bs _{The IrDA Interface is disabled after a reset and is enabled by setting the IRDAEN Bit in the}
O _{SFR named IRDACON (Table 68 on page 120). When IrDA is disabled, the UART1's RxD}
- _{and TxD signals will bypass the internal IrDA logic and instead they are routed directly to the}
) _{pins RxD1 and TxD1 respectively. When IrDA is enabled, the IrDA pulse shaping logic is}
t(s ^{active and resides between UART1 and the pins RxD1 and TxD1 as shown in Figure 35 on}
c _{page 119.}
du _{Table 68.}
ro _{Bit 7}
te ^{P –}
IRDACON register (SFR CEh, Reset Value 0Fh)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
IRDAEN PULSE CDIV4
CDIV3
CDIV2
Bit 1
CDIV1
Bit 0
CDIV0
soleTable 69. RDACON register bit definition
Ob ^Bit
Symbol
R/W
Definition
7
–
–
Reserved
IrDA Enable
6
IRDAEN
RW
0 = IrDA Interface is disabled
1 = IrDA is enabled, UART1 outputs are disconnected
from Port 1 (or Port 4)
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Doc ID 9685 Rev 7