UPSD3354DV-40U6 Datasheet, PDF (166/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
27.1.4
Secondary Flash memory
The smaller secondary Flash memory is also divided into equal sized sectors that are
individually selectable by the Decode PLD signals, named CSBOOTx, one signal for each
secondary Flash memory sector. Each sector can be located at any address within 8032
program address space (accessed with PSEN) or XDATA space (accessed with RD or WR)
as defined with PSDsoft Express. The user only has to specify an address range for each
segment, and specify if secondary Flash memory will reside in 8032 data or program
address space, and then PSEN, RD, or WR are automatically activated for the specified
range. 8032 firmware is easily programmed into secondary Flash memory using PSDsoft
Express and others. See Table 112 on page 166 for secondary Flash sector sizes.
27.1.5 SRAM
The SRAM is selected by a single signal, named RS0, from the Decode PLD. SRAM may be
located at any address within 8032 XDATA space (accessed with RD or WR), or optionally
within 8032 program address space (accessed with PSEN) to execute code from SRAM.
The default setting places SRAM in XDATA space only. These choices are specified using
PSDSoft Express, where the user specifies an SRAM address range. The user would also
) _{specify (at run-time) if SRAM will additionally reside in 8032 program address space, and}
t(s ^{then PSEN, RD, or WR are automatically activated for the specified range. See Table 112 on}
c page 166 for SRAM sizes.
du _{Table 112. UPSD33xx memory configuration}
ro _{Main Flash memory}
Secondary Flash memory
SRAM
bsolete ^{P Device}
Total Flash
size
(Kbytes)
Individual
sector size
(Kbytes)
Number of
sectors
(Sector
Select
signal)
Total Flash
size
(Kbytes)
Individual
sector size
(Kbytes)
Number of
sectors
(Sector Select
signal)
SRAM size
(Kbytes)
O _UPSD3312xx
64
) ^- UPSD3333xx
128
t(s ^UPSD3334xx
256
c _UPSD3354xx
256
16
4 (FS0-3)
16
16
8 (FS0-7)
32
32
8 (FS0-7)
32
32
8 (FS0-7)
32
8
2 (CSBOOT0-1)
2
8
4 (CSBOOT0-3)
8
8
4 (CSBOOT0-3)
8
8
4 (CSBOOT0-3)
32
Obsolete ^{Produ 27.1.6}
Runtime Control registers, CSIOP
A block of 256 bytes is decoded inside the PSD module for module control and status (see
Table 116 on page 180). The base address of these 256 locations is referred to in this data
sheet as csiop (Chip Select I/O Port), and is selected by the Decode PLD output signal,
CSIOP. The csiop registers are always viewed by the 8032 as XDATA, and are accessed
with RD and WR signals. The address range of CSIOP is specified using PSDsoft Express
where the user only has to specify an address range of 256 bytes, and then the RD or WR
signals are automatically activated for the specified range. Individual registers within this
block are accessed with an offset from the specified csiop base address. 39 registers are
used out of the 256 locations to control the output state of I/O pins, to read I/O pins, to set
the memory page, to control 8032 program and data address space, to control power
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Doc ID 9685 Rev 7