UPSD3354DV-40U6 Datasheet, PDF (62/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Interrupt system
UPSD33xx
Note:
interrupt flag is not cleared after servicing the interrupt, an unwanted interrupt will occur
upon exiting the ISR.
After the interrupt is serviced, the last instruction executed by the ISR is RETI. The RETI
informs the MCU that the ISR is no longer in progress and the MCU pops the top two bytes
from the stack and loads them into the PC. Execution of the interrupted program continues
where it left off.
An ISR must end with a RETI instruction, not a RET. An RET will not inform the interrupt
control system that the ISR is complete, leaving the MCU to think the ISR is still in progress,
making future interrupts impossible.
Table 18. Interrupt summary
Interrupt
source
Polling Vector
priority addr.
Flag bit name
(SFR.bit position)
1 = Intr pending
0 = No interrupt
Flag bit auto-
cleared
by hardware
Enable bit name
(SFR.bit position)
1 = Intr enabled
0 = Intr disabled
Priority bit name
(SFR.bit position)
1= high priority
0 = low priority
Reserved 0 (high) 0063h
t(s) ^External
Interrupt INT0
1
0003h
uc ^{Timer 0}
d Overflow
2 000Bh
ro _External
P _{Interrupt INT1}
3
0013h
te Timer 1
le ^Overflow
4 001Bh
so _UART0
5 0023h
Ob _{Timer 2}
- _Overflow
t(s) ^{or TX2 Pin}
6 002Bh
uc ^SPI
7 0053h
rod _Reserved
P _I2C
te _ADC
ole _PCA
8 0033h
9 0043h
10 003Bh
11 005Bh
Obs_{UART1 12 (low) 004Bh}
–
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3
TF1 (TCON.7)
RI (SCON0.0)
TI (SCON0.1)
TF2 (T2CON.7)
EXF2 (T2CON.6)
TEISF, RORISF,
TISF, RISF
(SPISTAT[3:0])
–
INTR (S1STA.5)
AINTF (ACON.7)
OFVx, INTFx
(PCASTA[0:7])
RI (SCON1.0)
–
Edge - Yes
Level - No
Yes
Edge - Yes
Level - No
Yes
No
No
Yes
–
Yes
No
No
No
–
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES0 (IE.4)
ET2 (IE.5)
ESPI (IEA.6)
–
EI²C (IEA.1)
EADC (IEA.7)
EPCA (IEA.5)
ES1 (IEA.4)
–
PX0 (IP.0)
PT0 (IP.1)
PX1 (IP.2)
PT1 (IP.3)
PS0 (IP.4)
PT2 (IP.5)
PSPI (IPA.6)
–
PI²C (IPA.1)
PADC (IPA.7)
PPCA (IPA.5)
PS1 (IPA.4)
TI (SCON1.1)
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Doc ID 9685 Rev 7