UPSD3354DV-40U6 Datasheet, PDF (189/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
The Error Flag Bit (DQ5) is set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte, or if the 8032 attempted to program bit to logic ’1’
when that bit was already programmed to logic ’0’ (must erase to achieve logic ’1’).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the byte that was written to Flash
memory with the byte that was intended to be written.
When using the Data Toggle method during an erase operation, Figure 61 on page 189 still
applies. the Toggle Flag Bit (DQ6) toggles until the erase operation is complete. A ’1’ on the
Error Flag Bit (DQ5) indicates a timeout condition on the Erase cycle, a ’0’ indicates no
error. The 8032 can read any location within the sector being erased to get the Toggle Flag
Bit (DQ6) and the Error Flag Bit (DQ5).
PSDsoft Express generates ANSI C code functions for implementation of these Data
Toggling algorithms.
Figure 61. Data Toggle flowchart
START
t(s) _READ
c _{DQ5 & DQ6}
rodu DQ= 6
NO
P ^TOGGLE
te ^YES
ole ^NO _DQ5
s = 1
b_YES
- ^OREAD DQ6
t(s) _DQ=6
NO
c _TOGGLE
du YES
ro _FAIL
PASS
te ^P AI01370B
sole 27.4.12 Ready/Busy (PC3)
Ob ^{This signal can be used to output the Ready/Busy status of a program or erase operation on}
either Flash memory. The output on the Ready/Busy pin is a ’0’ (Busy) when either Flash
memory array is being written, or when either Flash memory array is being erased. The
output is a ’1’ (Ready) when no program or erase operation is in progress. To activate this
function on this pin, the user must select the “Ready/Busy” selection in PSDsoft Express
when configuring pin PC3. This pin may be polled by the 8032 or used as a 8032 interrupt to
indicate when an erase or program operation is complete (requires routing the signal on PC
board from PC3 back into a pin on the MCU module). This signal is also available internally
Doc ID 9685 Rev 7
189/272