UPSD3354DV-40U6 Datasheet, PDF (92/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Supervisory functions
UPSD33xx
In this example,
t_{MACH_CYC} = 100ns (4 MCU_CLK periods x 25ns)
N_OVERFLOW = 2²⁴ = 16777216 up-counts
WDT_PERIOD = 100ns X 16777216 = 1.67 seconds
The actual value will be slightly longer due to PFQ/BC.
19.5.1 Firmware example
The following 8051 assembly code illustrates how to operate the WDT. A simple statement
in the reset initialization firmware enables the WDT, and then a periodic write to clear the
WDT in the main firmware is required to keep the WDT from overflowing. This firmware is
based on the example above (40 MHz f_OSC, CCON0 = 10h, BUSCON = C1h).
For example, in the reset initialization firmware (the function that executes after a jump to
the reset vector):
) ^{MOV AE, #AA}
; enable WDT by writing value to
; WDKEY other than 55h
t(s _{Somewhere in the flow of the main program, this statement will execute periodically to reset}
c _{the WDT before it’s timeout period of 1.67 seconds. For example:}
lete ^{Produ MOV A6, #00}
; reset WDT, loading 000000h.
; Counting will automatically
; resume as long as 55h in not in
; WDKEY
so ^{Table 50.}
- ^{Ob Bit 7}
WDKEY: Watchdog Timer Key register (SFR AEh, reset value 55h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDKEY[7:0]
t(s) _{Table 51. WDKEY register bit definition}
uc _{Bit Symbol R/W}
Definition
rod 55h disables the WDT from counting. 55h is automatically loaded in
this SFR after any reset condition, leaving the WDT disabled by
P _{[7:0] WDKEY W default.}
te _{Any value other than 55h written to this SFR will enable the WDT, and}
le counting begins.
Obso ^{Table 52. WDRST: Watchdog Timer Reset Counter register (SFR A6h, reset value}
00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDRST[7:0]
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Doc ID 9685 Rev 7