UPSD3354DV-40U6 Datasheet, PDF (236/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
27.5.4
Note:
4-pin JTAG ISP (default)
The four basic JTAG pins on Port C are enabled for JTAG operation at all times. These pins
may not be used for other I/O functions. There is no action needed in PSDsoft Express to
configure a device to use 4-pin JTAG, as this is the default condition. No 8032 firmware is
needed to use 4-pin ISP because all ISP functions are controlled from the external JTAG
program/test equipment. Figure 80 on page 236 shows recommended connections on a
circuit board to a JTAG program/test tool using 4-pin JTAG. It is required to connect the RST
output signal from the JTAG program/test equipment to the RESET_IN input on the
UPSD33xx. The RST signal is driven by the equipment with an Open Drain driver, allowing
other sources (like a push button) to drive RESET_IN without conflict.
The recommended pull-up resistors and decoupling capacitor are illustrated in Figure 80.
Figure 80. Recommended 4-pin JTAG connections
CIRCUIT
BOARD
t(s) ^UPSD33XX
c _{TMS - PC0}
u _{TCK - PC1}
rod ^{I/O - PC2}
GENERAL I/O - PC3
P _{GENERAL I/O - PC4}
te TDI - PC5
le TDO - PC6
o _{GENERAL I/O - PC7}
t(s) ^{- Obs} _RESETIN
Obsolete ^{Produc DEBUG}
100k
typical
JTAG
CONN.
TMS
TCK
GENERAL I/O
SIGNALS
0.01
µF
10k
100k
PUSH BUTTON
or ANY OTHER
RESET SOURCE
OPTIONAL
TEST POINT
TDI
TDO
V_CC(1,2)
JTAG
Programming
or Test
Equipment
Connects Here
GND
RST⁽³⁾
AI09185c
1. For 5 V UPSD33xx devices, pull-up resistors and V_CC pin on the JTAG connector should be connected to 5 V system V_DD.
2. For 3.3 V UPSD33xx devices, pull-up resistors and V_CC pin on the JTAG connector should be connected to 3.3 V system
V_CC.
3. This signal is driven by an Open-Drain output in the JTAG equipment, allowing more than one source to activate RESETIN.
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Doc ID 9685 Rev 7