UPSD3354DV-40U6 Datasheet, PDF (79/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
I/O ports of MCU module
Figure 16. MCU I/O cell block diagram for Port 1
Select_Alternate_Func
Digital_Alt_Func_Data_Out
P1.X SFR Read Latch
(for R-M-W instructions)
MCU_Reset
8032 Data Bus Bit
GPIO P1.X SFR
Write Latch
DELAY,
1 MCU_CLK
PRE
D
Q
SFR
P1.X
Latch _Q
IN 1 ^SEL
MUX Y
IN 0
DELAY,
1 MCU_CLK
VCC
VCC
WEAK
PULL-UP, B
HIGH
SIDE
VCC
STONGER
PULL-UP, A
P1.X Pin
LOW
SIDE
P1.X SFR Read Pin
Analog_Alt_Func_En
Digital_Pin_Data_In
) _{Analog_Pin_In}
uct(s Figure 17. MCU I/O cell block diagram for Port 3
rod Enable_I2C
P _{Select_Alternate_Func}
lete _{Digital_Alt_Func_Data_Out}
o _{P3.X SFR Read Latch}
s _{(for R-M-W instructions)}
Ob _{MCU_Reset}
t(s) ^{- 8032 Data Bus Bit}
c _{GPIO P3.X SFR}
u _{Write Latch}
Disables High-Side Driver
DELAY,
1 MCU_CLK
PRE
D
Q
SFR
P3.X
Latch _Q
IN 1 ^SEL
MUX Y
IN 0
DELAY,
1 MCU_CLK
rod _{P3.X SFR Read Pin}
Obsolete ^{P Digital_Pin_Data_In}
AI09600
VCC
VCC
WEAK
PULL-UP, B
HIGH
SIDE
VCC
STONGER
PULL-UP, A
P3.X Pin
LOW
SIDE
AI09601
Doc ID 9685 Rev 7
79/272