UPSD3354DV-40U6 Datasheet, PDF (94/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Standard 8032 timer/counters
20 Standard 8032 timer/counters
UPSD33xx
There are three 8032-style 16-bit Timer/Counter registers (Timer 0, Timer 1, Timer 2) that
can be configured to operate as timers or event counters.
There are two additional 16-bit Timer/Counters in the Programmable Counter Array (PCA),
see Section 26.1: PCA block on page 153 for details.
20.1 Standard timer SFRs
Timer 0 and Timer 1 have very similar functions, and they share two SFRs for control:
● TCON (Table 54 on page 95)
● TMOD (Table 56 on page 97).
Timer 0 has two SFRs that form the 16-bit counter, or that can hold reload values, or that
can scale the clock depending on the timer/counter mode:
● TH0 is the high byte, address 8Ch
t(s) ^{● TL0 is the low byte, address 8Ah}
c Timer 1 has two similar SFRs:
u _{● TH1 is the high byte, address 8Dh}
rod ^{● TL1 is the low byte, address 8Bh}
P _{Timer 2 has one control SFR:}
te ^{● T2CON (Table 58 on page 100)}
le _{Timer 2 has two SFRs that form the 16-bit counter, and perform other functions:}
so ● TH2 is the high byte, address CDh
b _{● TL2 is the low byte, address CCh}
- ^O Timer 2 has two SFRs for capture and reload:
) _{● RCAP2H is the high byte, address CBh}
t(s ● RCAP2L is the low byte, address CAh
Obsolete ^{Produc 20.2}
Clock sources
When enabled in the “Timer” function, the registers THx and TLx are incremented every
1/12 of the oscillator frequency (f_OSC). This timer clock source is not effected by MCU clock
dividers in the CCON0, stalls from PFQ/BC, or bus transfer cycles. Timers are always
clocked at 1/12 of f_OSC.
When enabled in the “Counter” function, the registers THx and TLx are incremented in
response to a 1-to-0 transition sampled at their corresponding external input pin: pin C0 for
Timer 0; pin C1 for Timer 1; or pin T2 for Timer 2. In this function, the external clock input pin
is sampled by the counter at a rate of 1/12 of f_OSC. When a logic '1' is determined in one
sample, and a logic '0' in the next sample period, the count is incremented at the very next
sample period (period1: sample=1, period2: sample=0, period3: increment count while
continuing to sample). This means the maximum count rate is 1/24 of the f_OSC. There are no
restrictions on the duty cycle of the external input signal, but to ensure that a given level is
sampled at least once before it changes, it should be active for at least one full sample
94/272
Doc ID 9685 Rev 7