UPSD3354DV-40U6 Datasheet, PDF (208/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
Figure 68. Detail of a single I/O port (typical of Ports A, B, C)
FROM AND-OR ARRAY
FROM PLD INPUT BUS
PT OUTPUT ENABLE (.OE)
PSD MODULE RESET
Q ^DIRECTION
CSIOP
REGIS-
TERS
8032
DATA
Q ^DRIVE
BITS _D
8032
WR
Q ^CONTROL
PSDsoft
OUTPUT
SELECT
WR RD PIO EN PSELx
I/O PORT
LOGIC
PERIPHERAL I/O
MODE SETS
DIRECTION
(PORT A ONLY)
DRIVE TYPE
OE
MUX
OUTPUT ENABLE
(MCUI/O)
Q ^{DATA OUT}
1
O
U
CLR
T
RESET
LATCHED ADDR BIT, PORT A or B
P
U
2T
OUTPUT
DRIVER
D BIT, PERIPH I/O MODE, Port A
TYPICAL
te ^{Product(s) FROMOMC}
sole ^ALLOCATOR
8032
DATA
BIT
1
P
D²
B₃
M4
U
X⁵
6
DIRECTION
DRIVE SELECT
CONTROL
DATA OUT (MCUI/O)
ENABLE OUT
DATA IN (MCUI/O)
8032 RD
ONE of 6
CSIOP
REGISTERS
FROM OMC OUTPUT
3_M
4^U
X
PERIPH I/O
DATA BIT
PIN
PORT A, B, C
INPUT
BUFFER
TO IMC
AI07873A
- ^Ob _{Table 130. Port operating modes}
t(s) ^{Port operating mode}
Port A (80-pin
only)
uc MCU I/O
Yes
rod ^{PLD I/O}
OMC MCELLAB Outputs
Yes
P _{OMC MCELLBC Outputs}
No
teExternal Chip-Select Outputs
No
lePLD Inputs
Yes
so ^{Latched Address Output}
Yes
Ob ^{Peripheral I/O mode}
Yes
Port B Port C Port D
Find it
Yes
Yes
Yes Section 27.4.37
Yes
No
No
Yes
Yes⁽¹⁾
No Section 27.4.38
No
No
Yes
Yes
Yes
Yes
Yes
No
No Section 27.4.39
No
No
No Section 27.4.40
JTAG ISP
No
No
Yes⁽²⁾
No
Note 27.4.41
on page 216
1. MCELLBC outputs available only on pins PC2, PC3, PC4, and PC7.
2. JTAG pins (PC0/TMS, PC1/TCK, PC5/TDI, PC6/TDO) are dedicated to JTAG pin functions (cannot be
used for general I/O).
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Doc ID 9685 Rev 7