UPSD3354DV-40U6 Datasheet, PDF (108/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Serial UART interfaces
UPSD33xx
addressed leave their SM2 bits set and go on about their business, ignoring the coming data
bytes.
SM2 has no effect in mode 0, and in mode 1, SM2 can be used to check the validity of the
stop bit. In a mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless
a valid stop bit is received.
21.2
Serial port control registers
The SFR SCON0 controls UART0, and SCON1 controls UART1, shown in Table 63 and
Table 65 on page 109. These registers contain not only the mode selection bits, but also the
9th data bit for transmit and receive (bits TB8 and RB8), and the UART Interrupt flags, TI
and RI.
Table 63. SCON0: Serial Port UART0 Control register (SFR 98h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
t(s) _{Table 64.}
uc _Bit
te ^Prod 7
bsole ₆
t(s) ^{- O} 5
Produc ₄
Obsolete³
SCON0 register bit definition
Symbol
R/W
Definition
SM0
SM1
SM2
REN
TB8
Serial Mode Select, See Table 62 on page 107. Important,
notice bit order of SM0 and SM1.
[SM0:SM1] = 00b, mode 0
R,W _{[SM0:SM1] = 01b, mode mode 1}
[SM0:SM1] = 10b, mode 2
[SM0:SM1] = 11b, mode 3
R,W
Serial Multiprocessor Communication Enable.
Mode 0: SM2 has no effect but should remain 0.
R,W ^{Mode 1: If SM2 = 0 then stop bit ignored. SM2 =1 then RI}
active if stop bit = 1.
Mode 2 and 3: Multiprocessor Comm Enable. If SM2=0, 9th bit
is ignored. If SM2=1, RI active when 9th bit = 1.
Receive Enable.
R,W If REN=0, UART reception disabled. If REN=1, reception is
enabled
R,W
TB8 is assigned to the 9th transmission bit in mode 2 and 3.
Not used in mode 0 and 1.
Mode 0: RB8 is not used.
Mode 1: If SM2 = 0, the RB8 is the level of the received stop
2
RB8
R,W bit.
Mode 2 and 3: RB8 is the 9th data bit that was received in
mode 2 and 3.
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Doc ID 9685 Rev 7