UPSD3354DV-40U6 Datasheet, PDF (131/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
I²C interface
23.10
I²C Data Shift register (S1DAT)
The S1ADR register (Table 76) holds a byte of serial data to be transmitted or it holds a
serial byte that has just been received. The MCU may access S1DAT while the SIOE is not
in the process of shifting a byte (the INTR flag indicates shifting is complete).
While transmitting, bytes are shifted out MSB first, and when receiving, bytes are shifted in
MSB first, through the Acknowledge Bit register as shown in Figure 39 on page 127.
23.10.1 Bus Wait condition
After the SIOE finishes receiving a byte in Receive mode, or transmitting a byte in Transmit
mode, the INTR flag (in S1STA) is set and automatically a wait condition is imposed on the
I²C bus (SCL held low by SIOE). In Transmit mode, this wait condition is released as soon
as the MCU writes any byte to S1DAT. In Receive mode, the wait condition is released as
soon as the MCU reads the S1DAT register.
This method allows the user to handle transmit and receive operations within an interrupt
service routine. The SIOE will automatically stall the I²C bus at the appropriate time, giving
the MCU time to get the next byte ready to transmit or time to read the byte that was just
) _received.
ct(s _{Table 76.}
rodu ^{Bit 7}
S1DAT: I²C Data Shift register (SFR DEh, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
S1DAT[7:0]
Bit 0
te ^P _{Table 77. S1DAT register bit definition}
ole Bit
Symbol
R/W
Function
Obs ^7:0
S1DAT[7:0]
R/W
Holds the data byte to be transmitted in Transmit mode, or it
holds the data byte received in Receiver mode.
Obsolete ^{Product(s) - 23.11}
I²C Address register (S1ADR)
The S1ADR register (Table 78) holds the 7-bit device address used when the SIOE is
operating as a Slave. When the SIOE receives an address from a Master, it will compare
this address to the contents of S1ADR, as shown in Figure 39 on page 127.
If the 7 bits match, the INTR Interrupt flag (in S1STA) is set, and the ADDR Bit (in S1CON) is
set. The SIOE cannot modify the contents S1ADR, and S1ADR is not used during Master
mode.
Table 78. S1ADR: I²C Address register (SFR DFh, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
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Doc ID 9685 Rev 7
131/272