UPSD3354DV-40U6 Datasheet, PDF (256/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

DC and AC parameters
UPSD33xx
Figure 90. Synchronous Clock mode timing – PLD
tCH
tCL
CLKIN
INPUT
REGISTERED
OUTPUT
tS
tH
tCO
AI02860
Table 176. CPLD macrocell synchronous Clock mode timing (5 V PSD module)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo _Slew
Off ^rate(1)
Unit
Maximum frequency
t(s) ^{external feedback}
1/(t_S+t_CO)
40.0
Produc ^fMAX
Maximum frequency
internal feedback
(f_CNT)
Maximum frequency
pipelined data
1/(t_S+t_CO–10)
1/(t_CH+t_CL)
66.6
83.3
te _{tS Input setup time}
12
ole ^tH ^{Input hold time}
0
bs ^{tCH Clock high time}
Clock Input
6
O t_CL Clock low time
Clock Input
6
- _{tCO Clock to output delay Clock Input}
t(s) ^{tARD CPLD array delay}
Any macrocell
uc ^tMIN
Minimum clock
period⁽²⁾
t_CH+t_CL
12
+ 2 + 10
13
–2
11 + 2
rod 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given
amount.
Obsolete ^{P 2. CLKIN (PD1) tCLCL = tCH + tCL.105}
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
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Doc ID 9685 Rev 7