UPSD3354DV-40U6 Datasheet, PDF (87/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
MCU bus interface
Table 47.
Bit 7
EPFQ
BUSCON: Bus Control register (SFR 9Dh, reset value EBh)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EBC
WRW[1:0]
RDW[1:0]
CW[1:0]
Table 48. BUSCON register bit definition
Bit
Symbol
R/W
Definition
Enable Pre-Fetch Queue
7
EPFQ
R,W 0 = PFQ is disabled
1 = PFQ is enabled (default)
Enable Branch Cache
6
EBC
R,W 0 = BC is disabled
1 = BC is enabled (default)
WR Wait, number of MCU_CLK periods for WR write bus
cycle during any MOVX instruction
00b: 4 clock periods
t(s) ^5:4
WRW[1:0]
R,W
01b: 5 clock periods
10b: 6 clock periods (default)
c _{11b: 7 clock periods}
du _{RD Wait, number of MCU_CLK periods for RD read bus cycle}
ro during any MOVX instruction
P 00b: 4 clock periods
te ^3:2
RDW[1:0]
R,W _{01b: 5 clock periods}
le ^{10b: 6 clock periods (default)}
o ^{11b: 7 clock periods}
s _{Code Wait, number of MCU_CLK periods for PSEN read bus}
b _{cycle during any code byte fetch or during any MOVC code}
O _{byte read instruction. Periods will increase with PFQ stall}
-_{00b: 3 clock periods - exception, for MOVC instructions this}
t(s) ^1:0
CW[1:0]
R,W _{setting results 4 clock periods}
01b: 4 clock periods
c _{10b: 5 clock periods}
Obsolete ^{Produ 11b: 6 clock periods (default)}
Doc ID 9685 Rev 7
87/272