UPSD3354DV-40U6 Datasheet, PDF (71/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Power saving modes
15.2 Power-down mode
Power-down mode will halt the 8032 core and all MCU peripherals (Power-down mode
blocks MCU_CLK and PERIPH_CLK). This is the lowest power state for the MCU module.
When the PSD module is also placed in Power-down mode, the lowest total current
consumption for the combined die is achieved for the UPSD33xx. See Section 27.1.16:
Power management on page 170 in the PSD module section for details on how to also place
the PSD module in Power-down mode. The sequence of 8032 instructions is important
when placing both modules into Power-down mode.
The instruction that sets the PD Bit in the SFR named PCON (Table 31 on page 72) is the
last instruction executed prior to the MCU module going into Power-down mode. Once in
Power-down mode, the on-chip oscillator circuitry and all clocks are stopped. The SFRs,
DATA, IDATA, and XDATA are preserved.
Power-down mode is terminated only by a reset from the supervisor, originating from the
RESET_IN_ pin, the low-Voltage Detect circuit (LVD), or a JTAG debug reset command.
Since the clock to the WTD is not active during Power-down mode, it is not possible for the
supervisor to generate a WDT reset.
) Table 29 on page 72 summarizes the status of I/O pins and peripherals during Idle and
t(s ^{Power-down modes on the MCU module. Table 30 on page 72 shows the state of 8032}
MCU address, data, and control signals during these modes.
roduc 15.3
Obsolete ^{Product(s) - Obsolete P} Note:
Reduced frequency mode
The 8032 MCU consumes less current when operating at a lower clock frequency. The MCU
can reduce it’s own clock frequency at run-time by writing to three bits, CPUPS[2:0], in the
SFR named CCON0 described in Table 27 on page 69. These bits effectively divide the
clock frequency (f_OSC) coming in from the external crystal or oscillator device. The clock
division range is from 1/2 to 1/2048, and the resulting frequency is f_MCU.
This MCU clock division does not affect any of the peripherals, except for the WTD. The
clock driving the WTD is the same clock driving the 8032 MCU core as shown in Figure 13
on page 69.
MCU firmware may reduce the MCU clock frequency at run-time to consume less current
when performing tasks that are not time critical, and then restore full clock frequency as
required to perform urgent tasks.
Returning to full clock frequency is done automatically upon an MCU interrupt, if the CPUAR
Bit in the SFR named CCON0 is set (the interrupt will force CPUPS[2:0] = 000). This is an
excellent way to conserve power using a low frequency clock until an event occurs that
requires full performance. See Table 27 on page 69 for details on CPUAR.
See the DC Specifications at the end of this document to estimate current consumption
based on the MCU clock frequency.
Some of the bits in the PCON SFR shown in Table 31 on page 72 are not related to power
control.
Doc ID 9685 Rev 7
71/272