UPSD3354DV-40U6 Datasheet, PDF (177/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
Figure 57. PSD module memory priority
Highest priority
Level 1
SRAM,
CSIOP, and
Peripheral I/O
mode
Level 2
Secondary
Flash memory
Level 3
Main Flash memory
Lowest priority
AI02867E
27.2.7
Obsolete ^{Product(s) - Obsolete Product(s) Note:}
The VM register
One of the csiop registers (the VM register) controls whether or not the 8032 bus control
signals RD, WR, and PSEN are routed to the main Flash memory, the secondary Flash
memory, or the SRAM. Routing of these signals to these PSM module memories
determines if memories reside in 8032 program address space, 8032 XDATA space, or both.
The initial setting of the VM register is determined by a choice in PSDsoft Express and
programmed into the UPSD33xx in a non-volatile fashion using JTAG. This initial setting is
loaded into the VM register upon power-up and also loaded upon any reset event. However,
the 8032 may override the initial VM register setting at run-time by writing to the VM register,
which is useful for IAP.
Table 115 on page 178 defines bit functions within the VM register.
Bit 7, PIO_EN, is not related to the memory manipulation functions of Bits 0, 1, 2, 3, and 4.
Also note that SRAM must at least always be in 8032 XDATA space (default condition). Bit 0
allows the user to optionally place SRAM into 8032 program space in addition to XDATA
space. CSIOP registers are always in XDATA space and cannot reside in program space.
Figure 58 on page 179 illustrates how the VM register affects the routing of RD, WR, and
PSEN to the memories on the PSD module. As an example, if we apply the value 0Ch to the
VM register to implement the memory map example shown in Figure 52 on page 171, then
the routing of RD, WR, and PSEN would look like that shown in Figure 59 on page 180.
In this example, the configuration is specified in PSDsoft Express and programmed into the
UPSD33xx using JTAG. Upon power-on or any reset condition, the non-volatile value 0Ch is
loaded into the VM register. At runtime, the value 0Ch in the VM register may be changed
(overridden) by the 8032 if desired to implement IAP or other functions.
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