UPSD3354DV-40U6 Datasheet, PDF (100/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Standard 8032 timer/counters
UPSD33xx
20.6.2
Note:
Auto-reload mode
In the Auto-reload mode, there are again two options, which are selected by the bit EXEN2
in T2CON. Figure 25 on page 104 shows Auto-reload mode.
If EXEN2 = 0, then when Timer 2 counts up and rolls over from FFFFh it not only sets the
interrupt flag TF2, but also causes the Timer 2 registers to be reloaded with the 16-bit value
contained in registers RCAP2L and RCAP2H, which are preset with firmware.
If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0
transition at external input T2X will also trigger the 16-bit reload and set the interrupt flag
EXF2. Again, firmware servicing the interrupt must read both TF2 and EXF2 to determine
the cause, and clear the flag(s) upon exit.
The UPSD33xx does not support selectable up/down counting in Auto-reload mode (this
feature was an extension to the original 8032 architecture).
Table 58. T2CON: Timer 2 Control register (SFR C8h, reset value 00h)
Bit 7
) ^TF2
Bit 6
EXF2
Bit 5
RCLK
Bit 4
TCLK
Bit 3
EXEN2
Bit 2
TR2
Bit 1
C/T2
Bit 0
CP/RL2
ct(s _{Table 59. T2CON register bit definition}
du _{Bit Symbol R/W}
Definition
ro _{Timer 2 flag, causes interrupt if enabled.}
P ₇
TF2
R,W TF2 is set by hardware upon overflow. Must be cleared by firmware.
te _{TF2 will not be set when either RCLK or TCLK =1.}
le _{Timer 2 flag, causes interrupt if enabled.}
so ₆
EXF2 R,W ^{EXF2 is set when a capture or reload is caused by a negative}
b _{transition on T2X pin and EXEN2 = 1. EXF2 must be cleared by}
O ^firmware.
- _{UART0 Receive Clock control.}
t(s) ^{5 RCLK(1) R,W When RCLK = 1, UART0 uses Timer 2 overflow pulses for its receive}
clock in modes 1 and 3. RCLK=0, Timer 1 overflow is used for its
c _{receive clock}
du UART0 Transmit Clock control.
ro ₄
TCLK⁽¹⁾ R,W ^{When TCLK = 1, UART0 uses Timer 2 overflow pulses for its transmit}
clock in modes 1 and 3. TCLK=0, Timer 1 overflow is used for transmit
P _clock
te _{Timer 2 External Enable.}
ole 3
EXEN2 R,W ^{When EXEN2 = 1, capture or reload results when negative edge on}
s ^{pin T2X occurs. EXEN2 = 0 causes Timer 2 to ignore events at pin}
b T2X.
O _{Timer 2 run control.}
2
TR2 R,W
1 = Timer/Counter 2 is on, 0 = Timer Counter 2 is off.
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Doc ID 9685 Rev 7