UPSD3354DV-40U6 Datasheet, PDF (217/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
mode, making the pin suitable for input mode (read by the input buffer shown in Figure 68 on
page 208). Figure 68 shows the three sources that can control the pin output enable signal:
a product term from AND-OR array; the csiop Direction register; or the Peripheral I/O Mode
logic (Port A only). The csiop Enable Out registers represent the state of the final output
enable signal for each port pin driver, and are defined in Table 150 through Table 153.
Table 146. Port A Pin Drive Select register (address = csiop + offset 08h)^(1)(2)(3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PA7
PA6
PA5
PA4
PA3
PA2
PA1
Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Slew Rate
1. Port A not available on 52-pin UPSD33xx devices
2. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull
3. Default state for register is 00h after reset or power-up
Bit 0
PA0
Slew Rate
Table 147. Port B Pin Drive Select register (address = csiop + offset 09h)⁽¹⁾⁽²⁾
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
t(s) ^PB7
PB6
PB5
PB4
PB3
PB2
PB1
c ^{Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Slew Rate}
u _{1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull}
rod ^{2. Default state for register is 00h after reset or power-up}
Bit 0
PB0
Slew Rate
te ^{P Table 148. Port C Pin Drive Select register (address = csiop + offset 16h)(1)(2)}
le ^{Bit 7}
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
so PC7
PC4
PC3
PC2
N/A (JTAG) N/A (JTAG)
N/A (JTAG) N/A (JTAG)
b _{Open Drain}
Open Drain Open Drain Open Drain
O _{1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull}
) ^{- 2. Default state for register is 00h after reset or power-up}
ct(s _{Table 149. Port D Pin Drive Select register (address = csiop + offset 17h)}⁽¹⁾⁽²⁾
du Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ro _PD2(3)
PD1
P N/A
N/A
N/A
N/A
N/A
Slew Rate Slew Rate
te _{1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull}
le _{2. Default state for register is 00h after reset or power-up}
Obso ^{3. Pin is not available on 52-pin UPSD33xx devices}
Bit 0
N/A
Table 150. Port A Enable Out register (address = csiop + offset 0Ch)⁽¹⁾⁽²⁾
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7 OE
PA6 OE
PA5 OE
PA4 OE
PA3 OE
PA2 OE
PA1 OE
PA0 OE
1. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)
2. Port A not available on 52-pin UPSD33xx devices
Doc ID 9685 Rev 7
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