UPSD3354DV-40U6 Datasheet, PDF (149/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Synchronous peripheral interface (SPI)
Table 91.
Bit 7
–
SPISTAT: SPI Interface Status register (SFR D3h, Reset Value 02h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
BUSY
TEISF RORISF
TISF
RISF
Table 92. SPISTAT register bit definition
Bit
Symbol
R/W
Definition
7-5
–
–
Reserved
SPI Busy
4
BUSY
R
0 = Transmit or Receive is completed
1 = Transmit or Receive is in process
Transmission End Interrupt Source flag
3
TEISF
R
0 = Automatically resets to '0' when firmware reads this
register
1 = Automatically sets to '1' when transmission end occurs
) ^{Receive Overrun Interrupt Source flag}
t(s ²
RORISF
R
0 = Automatically resets to '0' when firmware reads this
register
uc ^{1 = Automatically sets to '1' when receive overrun occurs}
d _{Transfer Interrupt Source flag}
ro _{0 = Automatically resets to '0' when SPITDR is full (just after}
P ₁
TISF
R
the SPITDR is written)
te ^{1 = Automatically sets to '1' when SPITDR is empty (just after}
le ^{byte loads from SPITDR into SPI shift register)}
o _{Receive Interrupt Source flag}
bs ₀
RISF
R
0 = Automatically resets to '0' when SPIRDR is empty (after
the SPIRDR is read)
Obsolete ^{Product(s) - O 1 = Automatically sets to '1' when SPIRDR is full}
Doc ID 9685 Rev 7
149/272