UPSD3354DV-40U6 Datasheet, PDF (259/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Figure 93. Input macrocell timing (product term clock)
t_INH
t_INL
PT CLOCK
t_IS
t_IH
INPUT
DC and AC parameters
OUTPUT
AI03101
t_INO
Table 180. Input macrocell timing (5 V PSD module)
Symbol
Parameter
Conditions Min
Max
PT Aloc
Turbo
Off
Unit
t_IS Input setup time
(1)
t(s) ^{tIH Input hold time}
(1)
t_INH NIB input high time
(1)
uc _{tINL NIB input low time}
(1)
rod ^t_INO
NIB input to combinatorial
delay
(1)
0
ns
15
+ 10
ns
9
ns
9
ns
34
+2
+ 10
ns
P _{1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to}
te ^tAVLX ^{and t}LXAX^.
sole ^{Table 181. Input macrocell timing (3V PSD module)}
Ob ^Symbol
Parameter
Conditions Min
Max
PT Aloc
Turbo
Off
Unit
) ^- t_IS
Input setup time
(1)
t(s ^tIH
Input hold time
(1)
uc ^tINH ^{NIB input high time}
(1)
d _{tINL NIB input low time}
(1)
Pro t_INO
NIB input to combinatorial
delay
(1)
0
ns
25
+ 15
ns
12
ns
12
ns
43
+4
+ 15
ns
te_{1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to}
Obsole ^{tAVLX and tLXAX.}
Doc ID 9685 Rev 7
259/272