UPSD3354DV-40U6 Datasheet, PDF (233/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
them an output. In this case, a weak external pull-up resistor (100KΩ minimum) should be
used on floating pins to avoid excessive current draw.
The pins on Ports 1, 3, and 4 of the 8032 MCU module do have weak internal pull-ups and
the inputs will not float, so no external pull-ups are needed.
Table 158. Function status during Power-up Reset, Warm Reset, Power-down mode
Port configuration or
registers
Power-Up Reset
Warm Reset
APD Power-down
mode
MCU I/O
Pins are in input mode Pins are in input mode
Pin logic state is
unchanged
Pin logic is valid after
Pin logic depends on
PLD I/O
internal PSD module
configuration bits are
loaded. Happens long
before RST is de-
Pin logic is valid and is
determined by PLD
logic equations
inputs to PLD (8032
addresses are blocked
from reaching PLD
inputs during power-
asserted
down mode)
Obsolete ^{Product(s) - Obsolete Product(s) 27.5.1}
Latched Address Out
mode
Pins are high
Impedance
Pins are high
Impedance
Pins logic state not
defined since 8032
address signals are
blocked
Peripheral I/O mode
Pins are high
Impedance
Pins are high
Impedance
Pins are high
Impedance
JTAG ISP and debug
JTAG channel is active JTAG channel is active JTAG channel is active
and available
and available
and available
PMMR0 and PMMR2
Cleared to 00h
Unchanged
Unchanged
Output of OMC Flip-
flops
Cleared to ’0’
Depends on .re and .pr Depends on .re and .pr
equations
equations
VM register⁽¹⁾
Initialized with value
that was specified in
PSDsoft
Initialized with value
that was specified in
PSDsoft
Unchanged
All other csiop registers
Cleared to 00h
Cleared to 00h
Unchanged
1. VM register Bit 7 (PIO_EN) and Bit 0 (SRAM in 8032 program space) are cleared to zero at power-up and
warm reset conditions.
JTAG ISP and JTAG debug
An IEEE 1149.1 serial JTAG interface is used on UPSD33xx devices for ISP (in-system
programming) of the PSD module, and also for debugging firmware on the MCU module.
IEEE 1149.1 Boundary Scan operations are not supported in the UPSD33xx.
The main advantage of JTAG ISP is that a blank UPSD33xx device may be soldered to a
circuit board and programmed with no involvement of the 8032, meaning that no 8032
firmware needs to be present for ISP. This is good for manufacturing, for field updates, and
for easy code development in the lab. JTAG-based programmers and debuggers for
UPSD33xx are available from STMicroelectronics and 3rd party vendors.
ISP is different than IAP. IAP involves the 8032 to program Flash memory over any interface
supported by the 8032 (e.g., UART, SPI, I2C), which is good for remote updates over a
communication channel. UPSD33xx devices support both ISP and IAP. The entire PSD
Doc ID 9685 Rev 7
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