UPSD3354DV-40U6 Datasheet, PDF (148/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Synchronous peripheral interface (SPI)
UPSD33xx
Table 87.
Bit 7
–
SPICON1: SPI Interface Control register 1 (SFR D7h, Reset Value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
–
TEIE
RORIE
TIE
RIE
Table 88. SPICON1 register bit definition
Bit
Symbol
R/W
Definition
7-4
–
–
Reserved
Transmission End Interrupt Enable
3
TEIE
RW 0 = Disable Interrupt for Transmission End
1 = Enable Interrupt for Transmission End
Receive Overrun Interrupt Enable
2
RORIE
RW 0 = Disable Interrupt for Receive Overrun
1 = Enable Interrupt for Receive Overrun
Transmission Interrupt Enable
) 1
TIE
RW 0 = Disable Interrupt for SPITDR empty
t(s ^{1 = Enable Interrupt for SPITDR empty}
c _{Reception Interrupt Enable}
u ₀
RIE
RW 0 = Disable Interrupt for SPIRDR full
rod ^{1 = Enable Interrupt for SPIRDR full}
te ^{P Table 89.}
ole _{Bit 7}
bs _DIV128
SPICLKD: SPI Prescaler (Clock Divider) register (SFR D2h, Reset Value
04h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIV64
DIV32
DIV16
DIV8
DIV4
–
–
) ^{- O} _{Table 90.}
t(s _Bit
duc 7
Pro ₆
lete5
Obso ⁴
SPICLKD register bit definition
Symbol
R/W
Definition
DIV128
DIV64
DIV32
DIV16
0 = No division
RW
1 = Divide f_OSC clock by 128
0 = No division
RW
1 = Divide f_OSC clock by 64
0 = No division
RW
1 = Divide f_OSC clock by 32
0 = No division
RW
1 = Divide f_OSC clock by 16
0 = No division
3
DIV8
RW
1 = Divide f_OSC clock by 8
0 = No division
2
DIV4
RW
1 = Divide f_OSC clock by 4
1-0
Not Used
–
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Doc ID 9685 Rev 7