UPSD3354DV-40U6 Datasheet, PDF (226/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
Table 155. Power Management Mode register PMMR2 (address = csiop + offset B4h)⁽¹⁾
Bit
num.
Bit name
Value
Description
Bit 0
X
0 Not used, and should be set to zero.
Bit 1
X
0 Not used, and should be set to zero.
Bit 2
Blocking Bit,
WR to
PLDs⁽²⁾
0 = on 8032 WR input to the PLD Input Bus is not blocked.
1 = off 8032 WR input to PLD Input Bus is blocked, saving power.
Bit 3
Blocking Bit,
RD to
PLDs⁽²⁾
0 = on 8032 RD input to the PLD Input Bus is not blocked.
1 = off 8032 RD input to PLD Input Bus is blocked, saving power.
Bit 4
Blocking Bit,
PSEN to
PLDs⁽²⁾
0 = on 8032 PSEN input to the PLD Input Bus is not blocked.
1 = off 8032 PSEN input to PLD Input Bus is blocked, saving power.
) ^{Bit 5}
duct(s ^{Bit 5}
Blocking Bit,
ALE to
PLDs⁽²⁾
Blocking Bit,
PC7 to
PLDs⁽²⁾
0 = on 8032 ALE input to the PLD Input Bus is not blocked.
1 = off 8032 ALE input to PLD Input Bus is blocked, saving power.
0 = on Pin PC7 input to the PLD Input Bus is not blocked.
1 = off Pin PC7 input to PLD Input Bus is blocked, saving power.
ro _{Bit 7}
X
0 Not used, and should be set to zero.
te ^{P 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the registers.}
le ^{2. Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation.}
bso ^{Table 156. Power Management Mode register PMMR3 (address = csiop + offset C7h)(1)}
O _Bit
- _num.
Bit name
Value
Description
t(s) ^{Bit 0}
X
0
Not used, and should be set to zero.
c _{Bit 1 FORCE_PD 0 = off APD counter will cause Power-down mode if APD is enabled.}
rodu ^{1 = on Power-down mode will be entered immediately regardless of APD activity.}
P _{Bit 3-7}
X
0
Not used, and should be set to zero.
Obsolete ^{1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the registers.}
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Doc ID 9685 Rev 7