UPSD3354DV-40U6 Datasheet, PDF (80/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

I/O ports of MCU module
UPSD33xx
Figure 18. MCU I/O cell block diagram for Port 4
Enable_Push_Pull
Select_Alternate_Func
Digital_Alt_Func_Data_Out
P4.X SFR Read Latch
(for R-M-W instructions)
MCU_Reset
8032 Data Bus Bit
GPIO P4.X SFR
Write Latch
For PCA Alternate Function
DELAY,
1 MCU_CLK
PRE
D
Q
SFR
P4.X
Latch _Q
IN 1 ^SEL
MUX Y
IN 0
DELAY,
1 MCU_CLK
VCC
VCC
WEAK
PULL-UP, B
HIGH
SIDE
VCC
STONGER
PULL-UP, A
P4.X Pin
LOW
SIDE
P4.X SFR Read Pin
Digital_Pin_Data_In
ct(s) _{Table 33.}
du _{Bit 7}
ro _P1.7
P1: I/O Port 1 register (SFR 90h, reset value FFh)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
P1.6
P1.5
P1.4
P1.3
P1.2
Bit 1
P1.1
AI09602
Bit 0
P1.0
lete ^{P Table 34. P1 register bit definition}
o _Bit
Symbol
R/W
Function⁽¹⁾
bs ₇
P1.7
R,W Port pin 1.7
O ₆
P1.6
R,W Port pin 1.6
) ^- ₅
P1.5
R,W Port pin 1.5
t(s 4
P1.4
R,W Port pin 1.4
uc ³
P1.3
R,W Port pin 1.3
d ₂
P1.2
R,W Port pin 1.2
ro ₁
P1.1
R,W Port pin 1.1
te ^{P 0}
P1.0
R,W Port pin 1.0
le^{1. Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have been set to '1' by}
Obso ^{firmware or by a reset event.}
80/272
Doc ID 9685 Rev 7