UPSD3354DV-40U6 Datasheet, PDF (66/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Interrupt system
UPSD33xx
Table 22. IEA register bit definition (continued)
Bit
Symbol
R/W
Function
4⁽¹⁾
ES1
R,W
Enable UART1 Interrupt
3
–
–
Reserved, do not set to logic '1.'
2
–
–
Reserved, do not set to logic '1.'
1⁽¹⁾
EI²C
R,W
Enable I²C Interrupt
0
–
–
Reserved, do not set to logic '1.'
1. 1 = Enable Interrupt, 0 = Disable Interrupt
Table 23. IP: Interrupt Priority register (SFR B8h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
PT2
PS0
PT1
PX1
PT0
PX0
) _{Table 24. IP register bit definition}
t(s Bit
Symbol
R/W
Function
uc ₇
–
–
Reserved
rod ⁶
–
–
Reserved
P ⁵⁽¹⁾
PT2
R,W
Timer 2 Interrupt priority level
te ⁴⁽¹⁾
PS0
R,W
UART0 Interrupt priority level
le 3⁽⁽¹⁾
PT1
R,W
Timer 1 Interrupt priority level
so ²⁽¹⁾
PX1
R,W
External Interrupt INT1 priority level
b ₁₍₁₎
PT0
R,W
Timer 0 Interrupt priority level
- ^O 0⁽¹⁾
PX0
R,W
External Interrupt INT0 priority level
) _{1. 1 = Assigns high priority level, 0 = Assigns low priority level}
ct(s _{Table 25.}
du _{Bit 7}
ro _PADC
IPA: Interrupt Priority Addition register (SFR B7h, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PSPI
PPCA
PS1
–
–
PI²C
–
lete ^{P Table 26.}
o _Bit
Obs ⁷⁽¹⁾
IPA register bit definition
Symbol
R/W
PADC
R,W
Function
ADC Interrupt priority level
6⁽¹⁾
PSPI
R,W
SPI Interrupt priority level
5⁽¹⁾
PPCA
R,W
PCA Interrupt level
4⁽¹⁾
PS1
R,W
UART1 Interrupt priority level
3
–
–
Reserved
2
–
–
Reserved
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Doc ID 9685 Rev 7