UPSD3354DV-40U6 Datasheet, PDF (218/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
Table 151. Port B Enable Out register (address = csiop + offset 0Dh)⁽¹⁾
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PB7 OE
PB6 OE
PB5 OE
PB4 OE
PB3 OE
PB2 OE
PB1 OE
1. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)
Bit 0
PB0 OE
Table 152. Port C Enable Out register (address = csiop + offset 1Ah)⁽¹⁾
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PC7 OE N/A (JTAG) N/A (JTAG) PC4 OE
PC3 OE
PC2 OE N/A (JTAG) N/A (JTAG)
1. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)
Table 153. Port D Enable Out register (address = csiop + offset 1Bh)⁽¹⁾
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
N/A
N/A
N/A
N/A
PD2 OE⁽²⁾ PD1 OE
N/A
) _{1. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)}
t(s ^{2. Pin is not available on 52-pin UPSD33xx devices}
Produc ^27.4.46
Individual port structures
Ports A, B, C, and D have some differences. The structure of each individual port is
described in the next sections.
Obsolete ^{Product(s) - Obsolete 27.4.47}
Port A structure
Port A supports the following operating modes:
● MCU I/O mode
● GPLD Output mode from Output Macrocells MCELLABx
● GPLD Input mode to Input Macrocells IMCAx
● Latched Address Output mode
● Peripheral I/O mode
Port A also supports Open Drain/Slew Rate output drive type options using csiop Drive
Select registers. Pins PA0-PA3 can be configured to fast slew rate, pins PA4-PA7 can be
configured to Open Drain mode. See Figure 73 on page 219 for details.
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Doc ID 9685 Rev 7